From dd48b176f31fb99218ff805000d7e630f00921de Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 11 Jun 2020 23:31:56 -0600 Subject: mb/google/dedede: Add support for 16 MiB flash map descriptor Upcoming variant boards will use 16 MiB SPI ROM. So add support for 16 MiB flash map descriptor. BUG=b:155107866,b:152981693 TEST=Build different variant boards. Ensure that waddledoo which is using 32 MiB SPI ROM boots. Cq-Depend: chrome-internal:3107306 Change-Id: I8a6868da3280a662ff3a30623804ff135e6cbfbc Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/42322 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- .../google/dedede/chromeos-dedede-16MiB.fmd | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd (limited to 'src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd') diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd new file mode 100644 index 0000000000..09b2abc208 --- /dev/null +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -0,0 +1,44 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x381000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x380000 + } + SI_BIOS@0x381000 0xc7f000 { + RW_LEGACY(CBFS)@0x0 0x1000 + RW_SECTION_A@0x1000 0x420000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x40ffc0 + RW_FWID_A@0x41ffc0 0x40 + } + RW_SECTION_B@0x421000 0x420000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x40ffc0 + RW_FWID_B@0x41ffc0 0x40 + } + RW_MISC@0x841000 0x3e000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x3000 + RW_SHARED@0x33000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x37000 0x2000 + RW_NVRAM(PRESERVE)@0x39000 0x5000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x87f000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} -- cgit v1.2.3