From ce529b631819574c3e1f6b10e60725df1638013e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 25 Feb 2019 23:40:40 -0600 Subject: mb/google/cyan: fix RAM training on edgar variant Adapted from Chromium commit 5351dc0d [Edgar: To set the RX ODT limit and dram geometry with RAMID detection] Several cyan variants require memory init parameters be passed to FSP for handling of specific Micron modules; without these, RAM init will fail when loading training data from the MRC cache, and boot will halt. This was missed when I upstreamed edgar along with the other cyan variants, so add the required memory init parameters for edgar as per its source Chromium branch. Test: build/boot on edgar board with affected Micron memory modules, verify boot successful with populated MRC cache. Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/31615 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../google/cyan/variants/edgar/Makefile.inc | 1 + .../google/cyan/variants/edgar/romstage.c | 47 ++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 src/mainboard/google/cyan/variants/edgar/romstage.c (limited to 'src/mainboard/google/cyan') diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index 2e8b02c64e..ad9ac8a422 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c new file mode 100644 index 0000000000..12fef77394 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) +{ + int ram_id = get_ramid(); + + /* + * RAMID = 5 - 4GiB Micron MT52L256M32D1PF-107 + * RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107 + */ + if (ram_id == 5 || ram_id == 7) { + + /* + * For new micron part, it requires read/receive + * enable training before sending cmds to get MR8. + * To override dram geometry settings as below: + * + * PcdDramWidth = x32 + * PcdDramDensity = 8Gb + * PcdDualRankDram = disable + */ + memory_params->PcdRxOdtLimitChannel0 = 1; + memory_params->PcdRxOdtLimitChannel1 = 1; + memory_params->PcdDisableAutoDetectDram = 1; + memory_params->PcdDramWidth = 2; + memory_params->PcdDramDensity = 3; + memory_params->PcdDualRankDram = 0; + } +} -- cgit v1.2.3