From b1e4bd0d28bb65474c0a954374124f21cac05972 Mon Sep 17 00:00:00 2001
From: Kenji Chen <kenji.chen@intel.com>
Date: Mon, 16 Nov 2015 17:08:32 +0800
Subject: Braswell: Separate L1 Sub State init procedure for boards.

Original-Reviewed-on: https://chromium-review.googlesource.com/312743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://review.coreboot.org/12750
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/mainboard/google/cyan/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mainboard/google/cyan')

diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index c5a1346979..5eb0815435 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_LPC_TPM
 	select SOC_INTEL_BRASWELL
 	select HAVE_ACPI_RESUME
+	select PCIEXP_L1_SUB_STATE
 
 config CHROMEOS
 	select LID_SWITCH
-- 
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