From aa8d7721d400c20b73a1de8036d45654bdc625ee Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 2 Sep 2019 15:01:56 +0800 Subject: lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/cyan/spd/spd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/cyan') diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 7c66e947fc..f73b9e6539 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -122,9 +122,9 @@ static void set_dimm_info(const uint8_t *spd, struct dimm_info *dimm) const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + int ranks = spd_ranks[(spd[DDR3_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[DDR3_ORGANIZATION] & 7]; + int busw = spd_busw[spd[DDR3_BUS_DEV_WIDTH] & 7]; void *hob_list_ptr; EFI_HOB_GUID_TYPE *hob_ptr; -- cgit v1.2.3