From 8fbfcc3a06d2dde8aa625db123b42cfe29aa0752 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 30 Mar 2020 23:20:32 -0500 Subject: mb/google/cyan: convert to overridetree Simply cyan variants by converting to overridetree format. A few differences were ignored as there appears to be no reason behind them: - cyan had PCIe RP2 enabled, but nothing is attached to it - kefka had the SPI 1 device disabled - reks, relm, and ultima had HSUART 1 disabled - edgar had I2C1 UPD disabled Test: build/boot cyan and edgar variants, verify everything still works Change-Id: I9928cc59adcfda4661ddfdfa95f53a7820053b4a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39964 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../google/cyan/variants/wizpig/overridetree.cb | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/mainboard/google/cyan/variants/wizpig/overridetree.cb (limited to 'src/mainboard/google/cyan/variants/wizpig/overridetree.cb') diff --git a/src/mainboard/google/cyan/variants/wizpig/overridetree.cb b/src/mainboard/google/cyan/variants/wizpig/overridetree.cb new file mode 100644 index 0000000000..5923462147 --- /dev/null +++ b/src/mainboard/google/cyan/variants/wizpig/overridetree.cb @@ -0,0 +1,32 @@ +chip soc/intel/braswell + + register "PcdEnableI2C0" = "1" # Touchscreen + + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "0" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "0" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "0" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "0" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbHsicPort" = "0" + + device domain 0 on + device pci 18.1 on end # 8086 22c1 - I2C Port 1: Touchscreen + end +end -- cgit v1.2.3