From fd7440d23126a0133e2563849fceec55a772de80 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 23 Apr 2019 12:21:17 -0500 Subject: soc/intel/braswell: add default option to use public FSP The current Braswell FSP 1.1 header in vendorcode/intel, for which there is no publicly available FSP binary, contains silicon init UPDs which are not found in the publicly available header/binary in the FSP Github repo. This prevents new boards from being added which use the public Braswell FSP header/binary. To resolve this, move the UPDs not found in the public header from the soc's chip.c to ramstage.c for the boards which use them. Add a Kconfig option to use the current non-public FSP header and select it for boards which need it (google/cyan variants); set the public FSP option as the default. Use the Kconfig option to set FSP_HEADER_PATH to ensure the correct header is used. Test: build google/cyan and intel/strago using non-public and public FSP header/binaries respectively. Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Nico Huber --- .../google/cyan/variants/kefka/ramstage.c | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 src/mainboard/google/cyan/variants/kefka/ramstage.c (limited to 'src/mainboard/google/cyan/variants/kefka/ramstage.c') diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c new file mode 100644 index 0000000000..d790708cce --- /dev/null +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void board_silicon_USB2_override(SILICON_INIT_UPD *params) +{ + if (SocStepping() >= SocD0) { + + //Follow Intel recommendation to set + //BSW D-stepping PERPORTRXISET 2 (low strength) + params->D0Usb2Port0PerPortRXISet = 2; + params->D0Usb2Port1PerPortRXISet = 2; + params->D0Usb2Port2PerPortRXISet = 2; + params->D0Usb2Port3PerPortRXISet = 2; + params->D0Usb2Port4PerPortRXISet = 2; + } +} -- cgit v1.2.3