From 73ac12196c61c8d0c21a54dfa87b858662d6859a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 23 May 2019 14:41:19 +0200 Subject: drivers/intel/fsp1.1: Simplify bootflow and clean up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This gets rid of the boilerplate back and forward calls between the SOC/FSP-driver code and mainboard code. Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961 Reviewed-by: Patrick Georgi Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/google/cyan/romstage.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/mainboard/google/cyan/romstage.c') diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index c877e42055..dea73e9eee 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -19,13 +19,6 @@ #include "spd/spd_util.h" -/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { -- cgit v1.2.3