From 4ba64c99e3afc7689eab1f498134c43d40248d25 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Fri, 26 Oct 2018 07:03:14 -0700 Subject: cheza: board-level GPIO support Change-Id: I64e79904c7ad95091ea29d9f80444c4e3b493471 Signed-off-by: T Michael Turney Reviewed-on: https://review.coreboot.org/c/29298 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/google/cheza/board.h | 30 ++++++++++++++++++++++++++++++ src/mainboard/google/cheza/bootblock.c | 3 ++- src/mainboard/google/cheza/chromeos.c | 27 +++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/cheza/board.h (limited to 'src/mainboard/google/cheza') diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h new file mode 100644 index 0000000000..f83ca06003 --- /dev/null +++ b/src/mainboard/google/cheza/board.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H +#define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H + +#include +#include + +#define GPIO_EC_IN_RW GPIO(11) +#define GPIO_AP_EC_INT GPIO(122) +#define GPIO_AP_SUSPEND GPIO(126) +#define GPIO_WP_STATE GPIO(128) +#define GPIO_H1_AP_INT GPIO(129) + +void setup_chromeos_gpios(void); + +#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H */ diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c index 6718d52156..c72856dee6 100644 --- a/src/mainboard/google/cheza/bootblock.c +++ b/src/mainboard/google/cheza/bootblock.c @@ -15,8 +15,9 @@ #include #include +#include "board.h" void bootblock_mainboard_init(void) { - + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index 538e46fa4b..1c2c4f5c5f 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -14,8 +14,35 @@ */ #include +#include +#include "board.h" + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP_STATE); +} + +void setup_chromeos_gpios(void) +{ + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + gpio_output(GPIO_AP_SUSPEND, 1); + gpio_input(GPIO_WP_STATE); + gpio_input_pullup(GPIO_H1_AP_INT); +} void fill_lb_gpios(struct lb_gpios *gpios) { + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, + {GPIO_WP_STATE.addr, ACTIVE_LOW, gpio_get(GPIO_WP_STATE), + "write protect"}, + {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -- cgit v1.2.3