From 8f2f22d25806a4547be1a1a125f153bb4b0fe581 Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Wed, 3 Aug 2016 12:15:22 +0530 Subject: skylake/devicetree: Add PIRQ Routing programming Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Signed-off-by: Barnali Sarkar Reviewed-on: https://review.coreboot.org/16044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Subrata Banik --- src/mainboard/google/chell/devicetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/mainboard/google/chell') diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 3f40449f0f..230a9a6d4d 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -56,6 +56,15 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | -- cgit v1.2.3