From 1a1515b949ef759729a217faf5e8274ec3f3cb5f Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Mon, 29 Feb 2016 13:20:44 +0530 Subject: skylake mainboards: Configure gpio PADRSTCFG to PLTRST With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki Original-Tested-by: Naresh Solanki Original-Reviewed-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi Original-Tested-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/13992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/chell/gpio.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google/chell') diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 0503e3e768..05897eb45a 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), /* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ @@ -155,14 +155,14 @@ static const struct pad_config gpio_table[] = { /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), -- cgit v1.2.3