From fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 19:11:50 +0100 Subject: nb/intel/sandybridge: Set up console in bootblock Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/butterfly/Makefile.inc | 2 + src/mainboard/google/butterfly/early_init.c | 169 +++++++++++++++++++++++++++ src/mainboard/google/butterfly/romstage.c | 174 ---------------------------- 3 files changed, 171 insertions(+), 174 deletions(-) create mode 100644 src/mainboard/google/butterfly/early_init.c delete mode 100644 src/mainboard/google/butterfly/romstage.c (limited to 'src/mainboard/google/butterfly') diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index fa9a4a9068..18f200647a 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -23,3 +23,5 @@ romstage-y += gpio.c smm-y += mainboard_smi.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c new file mode 100644 index 0000000000..d6566d1b09 --- /dev/null +++ b/src/mainboard/google/butterfly/early_init.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if CONFIG(CHROMEOS) +#include +#endif + +void mainboard_pch_lpc_setup(void) +{ + /* EC Decode Range Port60/64 and Port62/66 */ + /* Enable EC and PS/2 Keyboard/Mouse*/ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); +} + +void mainboard_late_rcba_config(void) +{ + u32 reg32; + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + + /* Disable unused devices (board specific) */ + reg32 = RCBA32(FD); + /* Disable PCI bridge so MRC does not probe this bus */ + reg32 |= PCH_DISABLE_P2P; + RCBA32(FD) = reg32; +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, 0, -1 }, /* P2: Camera (no OC) */ + { 0, 0, -1 }, /* P3: Empty */ + { 0, 0, -1 }, /* P4: Empty */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 0, 0, -1 }, /* P8: Empty */ + { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ + { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pei_data_template = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .ddr3lv_support = 0, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* enabled usb oc pin length */ + { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ + { 0, 0, 0x0000 }, /* P3: Empty */ + { 0, 0, 0x0000 }, /* P4: Empty */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 0, 4, 0x0000 }, /* P8: Empty */ + { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ + { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ + }, + .ddr_refresh_rate_config = 2, /* Force double refresh rate */ + }; + *pei_data = pei_data_template; +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c deleted file mode 100644 index e1d948d89f..0000000000 --- a/src/mainboard/google/butterfly/romstage.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if CONFIG(CHROMEOS) -#include -#endif - -void mainboard_pch_lpc_setup(void) -{ - /* EC Decode Range Port60/64 and Port62/66 */ - /* Enable EC and PS/2 Keyboard/Mouse*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); -} - -void mainboard_late_rcba_config(void) -{ - u32 reg32; - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ - { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, -1 }, /* P2: Camera (no OC) */ - { 0, 0, -1 }, /* P3: Empty */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 0, 0, -1 }, /* P8: Empty */ - { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ - { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - -void mainboard_config_superio(void) -{ -} - - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ - { 0, 0, 0x0000 }, /* P3: Empty */ - { 0, 0, 0x0000 }, /* P4: Empty */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 0, 4, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ - { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ - }; - *pei_data = pei_data_template; -} - -int mainboard_should_reset_usb(int s3resume) -{ - return !s3resume; -} -- cgit v1.2.3