From a911b758482025d46e132eeb2ed0279b65692075 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 5 Feb 2024 19:18:43 -0500 Subject: mb/*: Remove old USB configurations from SNB/bd82x6x boards Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/google/butterfly/devicetree.cb | 16 ---------------- src/mainboard/google/butterfly/early_init.c | 18 ------------------ 2 files changed, 34 deletions(-) (limited to 'src/mainboard/google/butterfly') diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index b8459c9009..cb34f3c55e 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -25,22 +25,6 @@ chip northbridge/intel/sandybridge # Force double refresh rate register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0080 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref peg10 off end # PCIe Bridge for discrete graphics diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index f63d3c3d75..8d07a38b14 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -44,24 +44,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, -1 }, /* P2: Camera (no OC) */ - { 0, 0, -1 }, /* P3: Empty */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 0, 0, -1 }, /* P8: Empty */ - { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ - { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mainboard_fill_pei_data(struct pei_data *pei_data) { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ -- cgit v1.2.3