From d55ed57c36e02b5fa1ddd3526309fcfa9eeefe88 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 26 Oct 2022 17:03:25 +0530 Subject: mb/google/brya : Set EPP value for Vell board The patch sets the EPP to 50% (0x80) for Vell. With EPP at 50%, the Vell system demonstrated better power improvement without sacrificing the performance. PLT Results(Perf) with EPP@40% and EPP@50%: EPP@40%: Device1-656 mins, Device2-664 mins. EPP@50%: Device1-678 mins, Device2-677 mins. In short, with EPP@50%, PLT KPI ran for more than 13 to 22mins compared to EPP@40%. Branch=firmware-brya-14505.B BUG=b:215526166 TEST=Verified code build for Vell board Signed-off-by: Sridhar Siricilla Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae Reviewed-on: https://review.coreboot.org/c/coreboot/+/68900 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/vell/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/google/brya') diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 98983ef03a..0c50eb422e 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -76,6 +76,10 @@ chip soc/intel/alderlake register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" register "sagv" = "SaGv_Enabled" + # Set EPP to 50%: 50 * 256 / 100 = 0x80 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x80" + # FIVR RFI Spread Spectrum 6% register "fivr_spread_spectrum" = "FIVR_SS_6" -- cgit v1.2.3