From ab58d2b488e72334458f774a254dbeffaa63a219 Mon Sep 17 00:00:00 2001
From: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Date: Mon, 18 Apr 2022 11:11:46 +0800
Subject: mb/google/brya/var/crota: Limit dram speed to 4800 MT/s

When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1)
page 121 recommends a maximum DRAM speed of 4800 MT/s.

BUG=b:229549930
BRANCH=none
TEST=build and pass memory training

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I38f0006d478702afb382d30338f20b46641964ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/crota/overridetree.cb | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard/google/brya')

diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb
index 23d7f3c69a..7a6b99e984 100644
--- a/src/mainboard/google/brya/variants/crota/overridetree.cb
+++ b/src/mainboard/google/brya/variants/crota/overridetree.cb
@@ -19,6 +19,8 @@ end
 
 chip soc/intel/alderlake
 
+	register "max_dram_speed" = "4800"
+
 	# Acoustic settings
 	register "acoustic_noise_mitigation" = "1"
 	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4"
-- 
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