From a77eb6e6c3d6b83bd63b6ea8dd9b3e22ed985347 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Mon, 17 May 2021 18:22:12 +0530 Subject: mb/google/brya: Disable dynamic GPIO PM for community 3 We recently added GPIO definition for PCIE vGPIO for Alder Lake. We also need to disable GPIO dynamic PM for this community which is already done for other communities as well. BUG=b:188392183 BRANCH=None TEST=Code compiles and Check if dynamic PM for GPIO COMM3 is also disabled Change-Id: I2f8645b8f4a9995e727a7623af97531c5de52892 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/54383 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/brya') diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 5f736719ff..cabbeea670 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -35,6 +35,7 @@ chip soc/intel/alderlake register "gpio_pm[COMM_0]" = "0" register "gpio_pm[COMM_1]" = "0" register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" -- cgit v1.2.3