From 93e8f8043417a6adfe909255fc2148563be7cf0d Mon Sep 17 00:00:00 2001 From: Johnny Li Date: Mon, 19 Sep 2022 17:31:24 +0800 Subject: =?UTF-8?q?mb/google/brya/var/crota:=20set=20tcc=5Foffset=20value?= =?UTF-8?q?=20to=201=20=E2=84=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set tcc_offset value to 1℃ in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:246913963 TEST=USE="project_crota project_brya" emerge-brya coreboot Signed-off-by: Johnny Li Change-Id: Ie2f60bed34fbd6fa3624be60138511a22b199a8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67708 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nick Vaccaro Reviewed-by: Sumeet R Pawnikar --- src/mainboard/google/brya/variants/crota/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/brya') diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 2843748bd3..245d553044 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -79,6 +79,7 @@ chip soc/intel/alderlake register "usb3_ports[0]" = "USB3_PORT_EMPTY" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "tcc_offset" = "1" # TCC of 99C device domain 0 on device ref dtt on -- cgit v1.2.3