From 7d85d43f18d9607a7d41eb401f8d096e28d98c18 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 22 Mar 2021 20:10:31 +0530 Subject: mb/google/brya: Update ddr config Fixed ddr config to override the FSP default value. BUG=b:182772421 TEST=Built image and passed memory training. Without this change: RcompTarget on Lpddr4x = { 40, 40, 30, 30, 30 } With this change: RcompTarget on Lpddr4x = { 40, 30, 30, 30, 30 } Signed-off-by: Eric Lai Signed-off-by: Subrata Banik Change-Id: Ib07ff36496828b5de78ed928b294a400ad08865f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51679 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/brya/variants/baseboard/memory.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/google/brya') diff --git a/src/mainboard/google/brya/variants/baseboard/memory.c b/src/mainboard/google/brya/variants/baseboard/memory.c index b0c150946d..2a0b6aca36 100644 --- a/src/mainboard/google/brya/variants/baseboard/memory.c +++ b/src/mainboard/google/brya/variants/baseboard/memory.c @@ -7,6 +7,14 @@ static const struct mb_cfg baseboard_memcfg = { .type = MEM_TYPE_LP4X, + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + /* DQ byte map */ .lpx_dq_map = { .ddr0 = { -- cgit v1.2.3