From 68f4f6ea49415453c994a4b9091f15de285a0407 Mon Sep 17 00:00:00 2001 From: Raihow Shi Date: Mon, 16 May 2022 09:26:23 +0800 Subject: mb/google/brask/variants/moli: enable USBA port 4 Moli has USBA port4 but Brask didn't use the port4, so enable USBA port4 in moli. BUG=b:232656163 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi Change-Id: I5308e3102ea9f0718802596a235c0a5cc42e30bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64370 Tested-by: build bot (Jenkins) Reviewed-by: Zhuohao Lee --- src/mainboard/google/brya/variants/moli/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/brya') diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index db472c557d..36938d7ae8 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -22,6 +22,7 @@ chip soc/intel/alderlake }" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port2 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3 + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9 register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP3 register "cnvi_bt_audio_offload" = "true" -- cgit v1.2.3