From 4fa835421690f233f739e18f6037f8549330e556 Mon Sep 17 00:00:00 2001 From: Won Chung Date: Tue, 19 Mar 2024 23:01:24 +0000 Subject: mb/google/brya: Correct _PLD values For Mithrax and Felwinter, port C1 is on the left side and port C2 is on the right side. Correct the values accordingly. The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports. BUG=b:321051330 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47 Signed-off-by: Won Chung Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Emilie Roberts --- src/mainboard/google/brya/variants/felwinter/overridetree.cb | 8 ++++---- src/mainboard/google/brya/variants/mithrax/overridetree.cb | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src/mainboard/google/brya') diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 40cbe4e46e..61cb50022a 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -377,7 +377,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port2 on end end @@ -385,7 +385,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -398,14 +398,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 6075351b25..61344d7e63 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -325,7 +325,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port2 on end end @@ -333,7 +333,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -346,14 +346,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -365,7 +365,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -379,7 +379,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end end -- cgit v1.2.3