From 394057e71522f9b351d60a2631ccc98d04c26f2e Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Tue, 26 Apr 2022 11:27:41 +0800 Subject: mb/google/brya/var/agah: Change Aux settings to TCSS port 2 Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2. Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I2d26777e850187aee0b676de13dff915474fed7b Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/agah/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/brya') diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index a7286a8572..ad23f7b6f1 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -31,8 +31,8 @@ chip soc/intel/alderlake }" register "sagv" = "SaGv_Enabled" - register "tcss_aux_ori" = "1" - register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "tcss_aux_ori" = "0x10" + register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN -- cgit v1.2.3