From 11fb6a87d7d19ba1bde52c0658bed70ca948fdc0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 16 Feb 2022 17:20:53 +0530 Subject: mb/google/brya/var/{gimble, gimble4es}: Use ACPI _PLD macro This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik Change-Id: I0274f03926d97fc543b98f3fb961580283202806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61825 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- .../google/brya/variants/gimble/overridetree.cb | 42 ++++------------------ .../google/brya/variants/gimble4es/overridetree.cb | 42 ++++------------------ 2 files changed, 12 insertions(+), 72 deletions(-) (limited to 'src/mainboard/google/brya') diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 5ecf9ccc9f..0d8b49b47e 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -265,24 +265,14 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -295,24 +285,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi @@ -325,12 +305,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port8 on end end chip drivers/usb/acpi @@ -344,12 +319,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port2 on end end end diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index d7ae9f3d8e..1ab9a7e6be 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -233,24 +233,14 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -263,24 +253,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi @@ -293,12 +273,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port8 on end end chip drivers/usb/acpi @@ -312,12 +287,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port2 on end end end -- cgit v1.2.3