From d4749184c242114ed2d43b2acdcbce9e568fe920 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 11 Feb 2021 13:43:02 -0700 Subject: mb/google/brya: Add EC I/O decode windows BUG=b:180013349 TEST=console shows successful EC <-> SoC communications Signed-off-by: Tim Wawrzynczak Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/brya/variants/baseboard/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/google/brya/variants') diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index b6b49dc361..c992f4fd2f 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,12 @@ chip soc/intel/alderlake device lapic 0 on end end + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 -- cgit v1.2.3