From ad3472a93c5bdcc63196344c5631ec9b1feac246 Mon Sep 17 00:00:00 2001 From: Amanda Huang Date: Thu, 20 Jun 2024 16:50:41 +0800 Subject: mb/google/trulo/var/orisa: Configure SEN_MODE_EC_PCH_INT_ODL as input Configure GPP_R2 as input, no pull according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ic678b77e5489f56d8ff92b265a6ca5852c0f7e8d Signed-off-by: Amanda Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/83142 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- src/mainboard/google/brya/variants/orisa/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/brya/variants') diff --git a/src/mainboard/google/brya/variants/orisa/gpio.c b/src/mainboard/google/brya/variants/orisa/gpio.c index f8d021a900..49fc02558e 100644 --- a/src/mainboard/google/brya/variants/orisa/gpio.c +++ b/src/mainboard/google/brya/variants/orisa/gpio.c @@ -122,7 +122,7 @@ static const struct pad_config gpio_table[] = { /* D1 : ISH_GP1 ==> SOC_GSEN2_INT# */ PAD_CFG_NF_LOCK(GPP_D1, NONE, NF1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> SEN_MODE_EC_PCH_INT_ODL */ - PAD_CFG_NF_LOCK(GPP_D2, NONE, NF1, LOCK_CONFIG), + PAD_CFG_GPI_LOCK(GPP_D2, NONE, LOCK_CONFIG), /* D3 : NC */ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D4 : NC */ -- cgit v1.2.3