From a9997f891facaf3c855d7f2c9c6840acbf101193 Mon Sep 17 00:00:00 2001 From: Shon Wang Date: Tue, 2 Jul 2024 16:47:53 +0800 Subject: mb/google/brask/var/bujia: Add wireless and memory thermal sensor Bujia has 4 thermal sensors, so add two missing sensors settings. BUG=b:351917517 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. check ACPI SSDT table have new TSR info. $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT check SSDT.dsl Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43 Signed-off-by: Shon Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/83302 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/bujia/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/google/brya/variants') diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index 4255296ff6..bf60101360 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -65,6 +65,8 @@ chip soc/intel/alderlake ## sensor information register "options.tsr[0].desc" = ""DRAM"" register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Wireless"" + register "options.tsr[3].desc" = ""Memory"" # TODO: below values are initial reference values only ## Active Policy @@ -84,6 +86,8 @@ chip soc/intel/alderlake [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), }" ## Critical Policy -- cgit v1.2.3