From a955efc190475bc1746c872395729a285c95d95e Mon Sep 17 00:00:00 2001
From: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Date: Tue, 5 Jul 2022 17:00:51 +0800
Subject: mb/google/brask/variants/moli: Add DPTF setting in Moli

DPTF Policy and temperature sensor values from thermal team.

BUG=b:236294162
TEST=emerge-brask coreboot

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
---
 .../google/brya/variants/moli/overridetree.cb      | 74 ++++++++++++++++++++++
 1 file changed, 74 insertions(+)

(limited to 'src/mainboard/google/brya/variants')

diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb
index 1c66d1ba19..9f2c22bda2 100644
--- a/src/mainboard/google/brya/variants/moli/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moli/overridetree.cb
@@ -35,6 +35,80 @@ chip soc/intel/alderlake
 	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"		# Disable TCP3
 	register "tcc_offset" = "0"	# TCC of 100C
 	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""SSD""
+				register "options.tsr[1].desc" = ""CPU_VR""
+				register "options.tsr[2].desc" = ""DIMM""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,		CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 15000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
-- 
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