From a874830dcc3a810aec6b3ccffcbb404feb028bf6 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 2 Dec 2022 14:08:33 +0800 Subject: mb/google/brya: Set power limit values for kano and zydron Add the RPL CPU power limits to kano and zydron's power limit table. BUG=b:261127266 BRANCH=brya TEST="emerge-brya coreboot chromeos-bootimage", flash zydron with image-zydron.serial.bin and verify zydron boots successfully to kernel. Change-Id: I369c5d7a9a3db0c3e7184a23b0f159ed715b5a50 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/70238 Reviewed-by: Eric Lai Reviewed-by: Tyler Wang Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/kano/ramstage.c | 2 ++ src/mainboard/google/brya/variants/zydron/ramstage.c | 2 ++ 2 files changed, 4 insertions(+) (limited to 'src/mainboard/google/brya/variants') diff --git a/src/mainboard/google/brya/variants/kano/ramstage.c b/src/mainboard/google/brya/variants/kano/ramstage.c index aa48a9db31..c0f126f624 100644 --- a/src/mainboard/google/brya/variants/kano/ramstage.c +++ b/src/mainboard/google/brya/variants/kano/ramstage.c @@ -9,6 +9,8 @@ const struct cpu_power_limits limits[] = { { PCI_DID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 20000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 20000, 43000, 43000, 105000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 12000, 15000, 40000, 40000, 114000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 12000, 15000, 40000, 40000, 114000 }, }; void variant_devtree_update(void) diff --git a/src/mainboard/google/brya/variants/zydron/ramstage.c b/src/mainboard/google/brya/variants/zydron/ramstage.c index aa48a9db31..c0f126f624 100644 --- a/src/mainboard/google/brya/variants/zydron/ramstage.c +++ b/src/mainboard/google/brya/variants/zydron/ramstage.c @@ -9,6 +9,8 @@ const struct cpu_power_limits limits[] = { { PCI_DID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 20000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 20000, 43000, 43000, 105000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 12000, 15000, 40000, 40000, 114000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 12000, 15000, 40000, 40000, 114000 }, }; void variant_devtree_update(void) -- cgit v1.2.3