From 9ffc9ebf250b57d22b06baa81e5a782ae95b72a1 Mon Sep 17 00:00:00 2001
From: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Date: Tue, 22 Mar 2022 18:12:47 +0530
Subject: mb/google/brya/baseboard/nissa: Enable DPTF for Nissa variants

BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board

Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
---
 src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mainboard/google/brya/variants')

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index 2ce9a7d68d..9267e21557 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -22,6 +22,9 @@ chip soc/intel/alderlake
 	# S0ix enable
 	register "s0ix_enable" = "1"
 
+	# DPTF enable
+	register "dptf_enable" = "1"
+
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"
 
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