From 8f6fd3264823cbf4b5e9093c4b847d9b72d00eb4 Mon Sep 17 00:00:00 2001 From: Casper Chang Date: Wed, 4 May 2022 10:43:48 +0800 Subject: mb/google/brask/variants/moli: correct tcss_usb3 port Correct tcss_usb3_port to meet Moli's schematic design. BUG=b:220814038 TEST=emerge-brask coreboot Signed-off-by: Casper Chang Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64039 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/moli/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/brya/variants') diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index e23107936e..24169c4d6e 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -144,7 +144,7 @@ chip soc/intel/alderlake end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port - use tcss_usb3_port2 as usb3_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end @@ -163,7 +163,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port3 on end end end end -- cgit v1.2.3