From 68bbbf8db2b59b7096eeb04be1d0a1d11fa2ea23 Mon Sep 17 00:00:00 2001 From: Frank Chu Date: Fri, 2 Dec 2022 11:38:44 +0800 Subject: mb/google/brya/var/marasov: Add the FIVR configurations This patch enables V1p05 and Vnn external bypass VRs for Marasov. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70233 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Dtrain Hsu Reviewed-by: Frank Chu Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/marasov/overridetree.cb | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/mainboard/google/brya/variants') diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 7ceafe66d7..09af8fa1ac 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -49,6 +49,20 @@ chip soc/intel/alderlake }, }" register "sagv" = "SaGv_Enabled" + + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, }" -- cgit v1.2.3