From 3eb17b91daac0b3acaffb01568d724d23c6f0eea Mon Sep 17 00:00:00 2001 From: Robert Chen Date: Thu, 9 Feb 2023 20:38:48 -0500 Subject: mb/google/brya/var/gladios: Update gpio table eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH. BUG=b:263548436 TEST=emerge-brask coreboot Change-Id: I610d53059e86945693bc5b3d7e43462e53640564 Signed-off-by: Robert Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/72940 Reviewed-by: Kevin Chiu Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/mainboard/google/brya/variants/gladios/gpio.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/mainboard/google/brya/variants') diff --git a/src/mainboard/google/brya/variants/gladios/gpio.c b/src/mainboard/google/brya/variants/gladios/gpio.c index 1dfef5ceb0..443d59c607 100644 --- a/src/mainboard/google/brya/variants/gladios/gpio.c +++ b/src/mainboard/google/brya/variants/gladios/gpio.c @@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = { /* B2 : VRALERT# ==> M2_SSD_PLA_L */ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> EMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ @@ -91,8 +91,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */ PAD_CFG_GPO(GPP_A21, 1, DEEP), - /* B3 : PROC_GP2 ==> EMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ @@ -136,8 +134,6 @@ static const struct pad_config early_gpio_table[] = { }; static const struct pad_config romstage_gpio_table[] = { - /* B3 : PROC_GP2 ==> EMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), }; -- cgit v1.2.3