From 2cb83125bb73f2c9b63519ccc05deb5c7adf690e Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 25 Mar 2024 08:57:09 +0900 Subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() The power_limits_config variable for ADL/RPL is array data, but we got soc_power_limits_config variable without its index. So correct the code to get the proper pointer of the data for current CPU SKU. I tried to override the PL4 value to 80W from 114W with following table in ramstage.c as a test for bug b/328729536. ``` const struct cpu_power_limits limits[] = { {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000}, } ``` And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool. - Before this patch: msr_pl4 was not changed, it's always 114 - After this patch: msr_pl4 was changed to 80 BUG=None BRANCH=None TEST=Built and tested the function could adjust PL4 on xol in local. Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436 Tested-by: build bot (Jenkins) Reviewed-by: Martin L Roth Reviewed-by: Eric Lai --- .../google/brya/variants/baseboard/brya/ramstage.c | 46 ++++++++++++++++++---- .../brya/variants/baseboard/hades/ramstage.c | 33 ++++++++++++++-- 2 files changed, 68 insertions(+), 11 deletions(-) (limited to 'src/mainboard/google/brya/variants') diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c index 9c2d4aa0b7..a7e5e8a521 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -11,11 +11,43 @@ WEAK_DEV_PTR(dptf_policy); +static struct soc_power_limits_config *get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + size_t i; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + uint16_t sa_pci_id; + u8 tdp; + + if (!sa) + return NULL; + + sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID); + + if (sa_pci_id == 0xffff) + return NULL; + + tdp = get_cpu_tdp(); + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_adl[i].limits]; + } + } + + return NULL; +} + void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { if (!num_entries) return; + struct soc_power_limits_config *soc_config = get_soc_power_limit_config(); + if (!soc_config) + return; + const struct device *policy_dev = DEV_PTR(dptf_policy); if (!policy_dev) return; @@ -29,20 +61,18 @@ void variant_update_power_limits(const struct cpu_power_limits *limits, size_t n for (size_t i = 0; i < num_entries; i++) { if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { struct dptf_power_limits *settings = &config->controls.power_limits; - config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, - MILLIWATTS_TO_WATTS); + MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", - limits[i].pl1_min_power, - limits[i].pl1_max_power, - limits[i].pl2_min_power, - limits[i].pl2_max_power, - limits[i].pl4_power); + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); } } } diff --git a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c index 4858eb70bd..7862dfe246 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c @@ -11,11 +11,40 @@ WEAK_DEV_PTR(dptf_policy); +static struct soc_power_limits_config *get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + size_t i; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + uint16_t sa_pci_id; + u8 tdp; + + if (!sa) + return NULL; + + sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID); + + tdp = get_cpu_tdp(); + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_adl[i].limits]; + } + } + + return NULL; +} + void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { if (!num_entries) return; + struct soc_power_limits_config *soc_config = get_soc_power_limit_config(); + if (!soc_config) + return; + const struct device *policy_dev = DEV_PTR(dptf_policy); if (!policy_dev) return; @@ -29,14 +58,12 @@ void variant_update_power_limits(const struct cpu_power_limits *limits, size_t n for (size_t i = 0; i < num_entries; i++) { if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { struct dptf_power_limits *settings = &config->controls.power_limits; - config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, - MILLIWATTS_TO_WATTS); + MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, limits[i].pl1_max_power, -- cgit v1.2.3