From 9c5a10714da47f9ace52d2b35d083c7202a246af Mon Sep 17 00:00:00 2001 From: Won Chung Date: Wed, 2 Feb 2022 22:30:53 +0000 Subject: mb/google/brya: Add custom PLD fields to devicetree for brya variants BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61571 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik Reviewed-by: EricR Lai --- .../google/brya/variants/taeko/overridetree.cb | 48 +++++++++++++++++++--- 1 file changed, 42 insertions(+), 6 deletions(-) (limited to 'src/mainboard/google/brya/variants/taeko') diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 05eca506be..2bddcd7c93 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -454,13 +454,25 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(1, 1)}" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(2, 1)}" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A end @@ -474,13 +486,25 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(1, 1)}" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(2, 1)}" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A end @@ -494,7 +518,13 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(4, 1)}" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -507,7 +537,13 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(4, 1)}" device ref usb3_port1 on end end end -- cgit v1.2.3