From 4902e9b35f1b62c2c28e582e33ad55d2543f1483 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 11 Jan 2023 17:41:37 -0600 Subject: drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flag Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) Reviewed-by: Martin L Roth --- src/mainboard/google/brya/variants/pujjo/overridetree.cb | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/google/brya/variants/pujjo') diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index dfbceec6d4..bacbbb0b15 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -353,7 +353,6 @@ chip soc/intel/alderlake register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end @@ -369,7 +368,6 @@ chip soc/intel/alderlake "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end -- cgit v1.2.3