From 2b523ce6316e5c5ec86fe812d739fe48ca81d83d Mon Sep 17 00:00:00 2001 From: Tarun Tuli Date: Mon, 29 Aug 2022 13:39:58 -0400 Subject: mb/google/brya: Invoke power cycle of FPMCU on startup Add functionality such that the FPMCU is power cycled and has its reset sequenced on boot. This has been added such that we do not need to update the bootblock. We are required to do this as bootblock exists in read-only flash for devices that have already been manufactured and so have no method of updating the sequencing there. Power remains off during coreboot (after briefly being turned on in the unchangeable bootblock). Once control is handed over to the Kernel, it takes care of sequencing the power and reset appropriately and ensures the FPMCU is unpowered for >200ms on boot. BUG=b:240626388 TEST=Confirmed FPMCU is still functional on Vell and Anahera. Confirmed power is off for approximately 6 seconds on boot (target >200ms). Confirmed reset is de-asserted approx 5ms after power application (target >2.5ms) Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086 Signed-off-by: Tarun Tuli Reviewed-on: https://review.coreboot.org/c/coreboot/+/66915 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/primus4es/gpio.c | 7 +++++++ src/mainboard/google/brya/variants/primus4es/overridetree.cb | 4 ++++ 2 files changed, 11 insertions(+) (limited to 'src/mainboard/google/brya/variants/primus4es') diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c index 5947b6e2e1..8eaad78a18 100644 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -138,8 +138,15 @@ static const struct pad_config early_gpio_table[] = { static const struct pad_config romstage_gpio_table[] = { /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), + + /* D1 : ISH_GP1 ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), }; diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index c6bb44f25b..c55fa11d98 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -284,6 +284,10 @@ chip soc/intel/alderlake register "compat_string" = ""google,cros-ec-spi"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" + register "enable_delay_ms" = "3" device spi 0 on end end # FPMCU end -- cgit v1.2.3