From 153e526f779323646225554f2643f8309743a0a7 Mon Sep 17 00:00:00 2001 From: John Su Date: Wed, 28 Sep 2022 10:25:30 +0800 Subject: mb/google/brya/var/mithrax: adjust I2C5 times for TP This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to follow I2C specification. I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us. I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us. BUG=b:249031186 BRANCH=brya TEST=EE check OK with test FW and TP function is normal. Signed-off-by: John Su Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67920 Reviewed-by: Ricky Chang Reviewed-by: Dtrain Hsu Tested-by: build bot (Jenkins) Reviewed-by: Frank Wu --- src/mainboard/google/brya/variants/mithrax/overridetree.cb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/brya/variants/mithrax') diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 589953506b..2755c704cf 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -81,7 +81,12 @@ chip soc/intel/alderlake .speed = I2C_SPEED_FAST, .rise_time_ns = 550, .fall_time_ns = 400, - .data_hold_time_ns = 50, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 70, + .sda_hold = 40, + } }, }" -- cgit v1.2.3