From 49d1cf9d49b77af6dc50371979c6d393365e6338 Mon Sep 17 00:00:00 2001 From: Daniel Peng Date: Wed, 29 Nov 2023 14:46:05 +0800 Subject: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance. The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W). BUG=b:312321601 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Built and booted into OS, and confirm MSR PL1=17W correctly. Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Signed-off-by: Daniel Peng Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335 Reviewed-by: Eric Lai Reviewed-by: Daniel Peng Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/marasov/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/google/brya/variants/marasov/overridetree.cb') diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index a8c1c06152..6c1f3f9341 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -134,6 +134,12 @@ chip soc/intel/alderlake register "tcc_offset" = "5" # TCC of 100 + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 17, + .tdp_pl2_override = 55, + .tdp_pl4 = 114, + }" + device domain 0 on device ref igpu on chip drivers/gfx/generic -- cgit v1.2.3