From 1c25808f0bd5509eb438063c26b58134d8f54ba9 Mon Sep 17 00:00:00 2001 From: Tarun Tuli Date: Thu, 20 Apr 2023 18:01:33 +0000 Subject: mb/google/brya/variants/hades: Swap LAN and SD Card PCIE Ports To aid in layout, the PCI ports for LAN and SD card were swapped. SD Card is now on RP3 (clksrc 4) LAN is now on RP8 (clksrc 3) BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Eric Lai --- .../google/brya/variants/hades/overridetree.cb | 36 +++++++++++----------- 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'src/mainboard/google/brya/variants/hades') diff --git a/src/mainboard/google/brya/variants/hades/overridetree.cb b/src/mainboard/google/brya/variants/hades/overridetree.cb index 9c9171c458..1412a1ff6a 100644 --- a/src/mainboard/google/brya/variants/hades/overridetree.cb +++ b/src/mainboard/google/brya/variants/hades/overridetree.cb @@ -211,10 +211,27 @@ chip soc/intel/alderlake end end device ref pcie_rp3 on - # Enable PCIE 3 using clk 4 + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + # Enable SD Card PCIE 3 using clk 4 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 4, .clk_req = 4, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE3 SD card + device ref pcie_rp4 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 on + # Enable PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip drivers/net @@ -225,23 +242,6 @@ chip soc/intel/alderlake device pci 00.0 on end end end #RTL8111H Ethernet NIC - device ref pcie_rp4 off end - device ref pcie_rp6 off end - device ref pcie_rp7 off end - device ref pcie_rp8 on - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" - register "srcclk_pin" = "3" - device generic 0 on end - end - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card device ref pcie_rp9 on # Enable NVMe PCIE 9 using clk 1 register "pch_pcie_rp[PCH_RP(9)]" = "{ -- cgit v1.2.3