From 1d886639ce680010a21e64d7122dfcfa92a9f505 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Thu, 20 Jan 2022 14:01:34 +0530 Subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 Gimble does not use WWAN and TCP Port 1 according to the schematics. Hence disabling it. BUG=b:216533766 TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled Signed-off-by: Meera Ravindranath change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Sridhar Siricilla Reviewed-by: Nick Vaccaro --- src/mainboard/google/brya/variants/gimble/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/brya/variants/gimble/overridetree.cb') diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 23071fe97a..408d380ce2 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -38,6 +38,7 @@ chip soc/intel/alderlake register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -121,6 +122,7 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref pcie_rp6 off end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" -- cgit v1.2.3