From 40d3409dab132eb292eb4d46064168731c575734 Mon Sep 17 00:00:00 2001 From: Raymond Chung Date: Tue, 25 Oct 2022 11:01:09 +0800 Subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. BUG=b:255399229, b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and pass MRC memory training Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806 Tested-by: build bot (Jenkins) Reviewed-by: Derek Huang Reviewed-by: Zhuohao Lee --- .../google/brya/variants/gaelin/Makefile.inc | 1 + src/mainboard/google/brya/variants/gaelin/memory.c | 40 ++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 src/mainboard/google/brya/variants/gaelin/Makefile.inc create mode 100644 src/mainboard/google/brya/variants/gaelin/memory.c (limited to 'src/mainboard/google/brya/variants/gaelin') diff --git a/src/mainboard/google/brya/variants/gaelin/Makefile.inc b/src/mainboard/google/brya/variants/gaelin/Makefile.inc new file mode 100644 index 0000000000..fd45b948ff --- /dev/null +++ b/src/mainboard/google/brya/variants/gaelin/Makefile.inc @@ -0,0 +1 @@ +romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/gaelin/memory.c b/src/mainboard/google/brya/variants/gaelin/memory.c new file mode 100644 index 0000000000..98b655c100 --- /dev/null +++ b/src/mainboard/google/brya/variants/gaelin/memory.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {50, 20, 25, 25, 25}, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; + spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; +} -- cgit v1.2.3