From 6f73a202d3df000fb2fd83080e0b148add344485 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 4 Feb 2022 12:45:37 -0700 Subject: drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to drivers Some non-SoC code might want to know whether or not the CNVi DDR RFIM feature is enabled. Also note that future SoCs may also support this feature. To make the CnviDdrRfim property generic, move it from soc/intel/alderlake to drivers/wifi/generic instead. Signed-off-by: Tim Wawrzynczak Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Varshit B Pandya --- src/mainboard/google/brya/variants/brya0/overridetree.cb | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/mainboard/google/brya/variants/brya0') diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 60d04696f7..f621b127aa 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -45,9 +45,6 @@ chip soc/intel/alderlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - # Enable CNVi DDR RFIM - register "CnviDdrRfim" = "1" - # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ @@ -187,6 +184,7 @@ chip soc/intel/alderlake device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end end -- cgit v1.2.3