From 6e4b81c20a2966e5c2718e564896ad554b05aede Mon Sep 17 00:00:00 2001 From: Alan Huang Date: Wed, 12 Jan 2022 13:21:09 +0800 Subject: Revert "mb/google/brya/var/brask: Configure the ISOLATE pin of LAN" This reverts commit 2bf2e6d1ccd87cdd8d9c189972eae89e47e542c8. According to the latest schematics, Brask supports D3-Hot for RTL8125 and does not need to operate the ISOLATE pin. BUG=b:193750191 BRANCH=None TEST=emerge-brask coreboot chromeos-bootimage Test with command suspend_stress_test Change-Id: Ica6bfb810887861f6b17ff527373824547e2406c Signed-off-by: Alan Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/61023 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/brask/overridetree.cb | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mainboard/google/brya/variants/brask') diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index b9c8edbe4f..3aeca90d7f 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -81,10 +81,6 @@ chip soc/intel/alderlake end device ref pcie_rp7 on chip drivers/net - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" register "wake" = "GPE0_DW0_07" register "led_feature" = "0xe0" register "customized_led0" = "0x23f" -- cgit v1.2.3