From 36721a483b9dffbae7cab37b18ae18a70c986af2 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 7 Oct 2021 16:02:11 -0600 Subject: mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables Before attempting another commit 6260bf71 ("vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants all program EC_IN_RW as an input GPIO in bootblock so that it can be read from in verstage. Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai Reviewed-by: Hsuan-ting Chen --- src/mainboard/google/brya/variants/brask/gpio.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/brya/variants/brask') diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c index 7bbe15551b..1f1d409f25 100644 --- a/src/mainboard/google/brya/variants/brask/gpio.c +++ b/src/mainboard/google/brya/variants/brask/gpio.c @@ -27,6 +27,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D2, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ -- cgit v1.2.3