From 0b108a14c09eafcd074ac039d3967e13ce9b9d5b Mon Sep 17 00:00:00 2001 From: Zhuohao Lee Date: Wed, 23 Feb 2022 15:22:19 +0800 Subject: mb/google/brask: Update PCH power cycle related durations The power rails discharge time of brask has been measured, the longest discharge time of the power rails are smaller than 150ms so it is safe to set the pwr_cyc_dur to 1 second. Since the brask is derived from the brya, we could apply the same setting from the brya. The setting is copied from commit dee834aa. BUG=b:214454454 BRANCH=firmware-brya-14505.B TEST=`test_that firmware_ECPowerButton` passed. Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d Signed-off-by: Zhuohao Lee Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/google/brya/variants/baseboard') diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index ec6fd96a34..98dd3a5fec 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -61,6 +61,12 @@ chip soc/intel/alderlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" + # HD Audio register "PchHdaDspEnable" = "1" register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" -- cgit v1.2.3