From 0a3bbe8645bbd88285f3128d9c2f49af4fb5535b Mon Sep 17 00:00:00 2001 From: Usha P Date: Mon, 9 May 2022 08:36:51 +0530 Subject: mb/google/brya: Set eMMC dll tuning parameters for Nissa Add support for MB level dll tuning. This patch sets the eMMC dll tuning parameters to default values needed. There was issue observed on some eMMC devices which failed to boot in HS400 mode.EV team suggested the intermediate eMMC dll tuning parameters that needs to be set. We observed these values helped to fix the issue. While we get the verified default values set from FSP directly, adding it here to use it as the custom dll values needed. BUG=b:230403441 TEST=Build and boot nivviks board. Verify the eMMC dll parameters are overridden. [INFO ] usha: After override dll_params [INFO ] usha: emmc_tx_cmd_cntl=505 [INFO ] usha: emmc_tx_data_cntl1=909 [INFO ] usha: emmc_tx_data_cntl2=1c2a2828 [INFO ] usha: emmc_rx_cmd_data_cntl1=1c1b1d3c [INFO ] usha: emmc_rx_cmd_data_cntl2=10049 [INFO ] usha: emmc_rx_strobe_cntl=11515 Signed-off-by: Usha P Change-Id: I27771b663ce9808e5a5ef4b36c136ad78f924376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64203 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Reka Norman Reviewed-by: Kangheui Won --- .../google/brya/variants/baseboard/nissa/devicetree.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/mainboard/google/brya/variants/baseboard') diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 9267e21557..83cd62fad8 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -31,6 +31,16 @@ chip soc/intel/alderlake # eMMC HS400 register "emmc_enable_hs400_mode" = "1" + #eMMC DLL tuning parameters + #Adding the intermediate eMMC DLL tuning override values + #TODO SoC implementation with the finalized verified values from EV Team + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D3C" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10049" + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 -- cgit v1.2.3