From 914ea8e5302a61cac9c81df9aad1d9967d844f18 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 18 Feb 2021 09:40:15 -0700 Subject: mb/google/brya: Implement SLP_S0_GATE signal The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to provide an indication to the rest of the platform when the system is entering its software-initiated low-power state (i.e. S0ix). This lets the platform distinguish between opportunistic S0ix entry and the runtime suspend mechanism. BUG=b:180401723 TEST=abuild Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881 Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- .../google/brya/variants/baseboard/include/baseboard/gpio.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google/brya/variants/baseboard/include') diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index 96e88b56d1..578fac9de9 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -7,12 +7,14 @@ #include /* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI +#define EC_SCI_GPI GPE0_ESPI /* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */ -#define GPE_EC_WAKE GPE0_DW2_17 +#define GPE_EC_WAKE GPE0_DW2_17 /* WP signal to PCH */ -#define GPIO_PCH_WP GPP_E15 +#define GPIO_PCH_WP GPP_E15 /* EC in RW or RO */ -#define GPIO_EC_IN_RW GPP_F18 +#define GPIO_EC_IN_RW GPP_F18 +/* Used to gate SoC's SLP_S0# signal */ +#define GPIO_SLP_S0_GATE GPP_F9 #endif /* __BASEBOARD_GPIO_H__ */ -- cgit v1.2.3