From 0dcdb217cf4fe1d2e2055994930eda618e9fe892 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 13 Aug 2021 08:31:52 +0200 Subject: soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Tim Crawford Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/google/brya/variants/baseboard/brask') diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index eb85cb5323..d19f627393 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -83,14 +83,12 @@ chip soc/intel/alderlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | #| I2C3 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | #+-------------------+---------------------------+ - register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, -- cgit v1.2.3