From a52b9c3a40dd082213b419f62d6ae3e1e071363b Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 6 Jan 2022 08:35:56 -0700 Subject: mb/google/brya: Move gpio_pm settings for brya variants to baseboards The factory versions (minor version 22) of cr50 FW have an issue with producing short interrupt pulses, which can be missed by the ADL PCH if autonomous GPIO power management is enabled, therefore instead of continually adding the setting to all the variants, move it to the baseboard instead. Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/anahera4es/overridetree.cb | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'src/mainboard/google/brya/variants/anahera4es') diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index 616224d09e..0b6db9f95e 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -22,17 +22,6 @@ fw_config end end chip soc/intel/alderlake - # This disables autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ -- cgit v1.2.3