From d5de10f02ee3c344f81a39428b60114c521b4597 Mon Sep 17 00:00:00 2001 From: Jing Tong Date: Mon, 1 Jul 2024 13:42:33 +0800 Subject: mb/google/brox/var/lotso: Tune I2C frequency for 400 kHz Before: I2C0 - 401kHz I2C4 - 405kHz After: I2C0 - 392kHz I2C4 - 395kHz HW: Change R8409/R8411 to 33ohm. BUG=b:349743464,b:349735055 TEST=emerge-brox sys-boot/coreboot Test pass by EE Change-Id: I985837b1b80e973f148529b446905580c0f95e98 Signed-off-by: Jian Tong Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Kun Liu --- src/mainboard/google/brox/variants/lotso/overridetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/mainboard/google/brox') diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 274e22c106..187840f1ce 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -48,6 +48,22 @@ chip soc/intel/alderlake register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable TCP0 register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP2 + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 350, + .data_hold_time_ns = 400, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 110, + .data_hold_time_ns = 100, + }, + }" + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoPci, -- cgit v1.2.3