From 3738e7408d6b12fcc4e29aeda5973e632198a344 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Sun, 7 Jan 2024 23:01:38 -0800 Subject: mb/google/brox: Fix error in DDR DQS config The DQS mapping for DIMM idx 6 was discovered to be incorrect to what was in the schematics. Correcting the mistake in this CL. BUG=b:311450057,b:300690448 BRANCH=None TEST=tested on device and it passed memory training Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Ivy Jian --- src/mainboard/google/brox/variants/baseboard/brox/memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/brox') diff --git a/src/mainboard/google/brox/variants/baseboard/brox/memory.c b/src/mainboard/google/brox/variants/baseboard/brox/memory.c index 4b03e21423..05434b1bef 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/memory.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/memory.c @@ -53,7 +53,7 @@ static const struct mb_cfg baseboard_memcfg = { .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, -- cgit v1.2.3