From 5e8b7963538bf125e5b743e7a9a1e995ef6298c6 Mon Sep 17 00:00:00 2001 From: Ren Kuo Date: Tue, 10 Sep 2024 12:30:46 +0800 Subject: mb/google/brox/var/jubilant: Enable ASPM for PCIe4 SSD of CPU Enable ASPM of CPU PCIe4 for SSD to improve power consumption. BUG=b:364441213 BRANCH=None TEST="sh -c 'lspci -vvnn || lspci -nn'" 01:00.0 Non-Volatile memory controller LnkCtl: ASPM L1 Enabled Change-Id: I4380bb8748f2847b1824e20edb19578c7aedfe4f Signed-off-by: Ren Kuo Reviewed-on: https://review.coreboot.org/c/coreboot/+/84279 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Subrata Banik --- src/mainboard/google/brox/variants/jubilant/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/brox/variants') diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 52a3236d38..2e7234dbd4 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -275,6 +275,7 @@ chip soc/intel/alderlake .clk_req = 3, .clk_src = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, }" probe STORAGE STORAGE_NVME probe unprovisioned -- cgit v1.2.3